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spoc - BTS5572E spi power controller data sheet, rev. 1.0, may 2008 automotive power
data sheet 2 rev. 1.0, 2008-05-15 spoc - BTS5572E table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 pin assignment spoc - BTS5572E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 power supply modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 power stage output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 over load protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 loss of v bb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 diagnosis word at spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 load current sense diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 switch bypass diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.5 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.5 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.6 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 package outlines spoc - BTS5572E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table of contents
pg-dso-36-36 type package marking spoc - BTS5572E pg-dso-36-36 BTS5572E data sheet 3 rev. 1.0, 2008-05-15 spi power controller for advanced light control with integrated led mode spoc - BTS5572E 1overview features ? 8 bit serial peripheral interface (daisy chain capable spi) for control and diagnosis ? cmos compatible parallel input pins for each channel provide direct pwm operation ? selectable and- / or-combination for parallel inputs (pwm control) ? very low stand-by current ? enhanced electromagnet ic compatibility (emc) for bulbs as well as led ? stable behavior at under voltage ? device ground independent from load ground ? green product (rohs-compliant) ? aec qualified description the spoc - BTS5572E is a five channel high-side smar t power switch in pg-dso-36-36 package providing embedded protective functions. it is specially design ed to control standard exterior lighting in automotive applications. in order to use the same hardware, the devic e can be configured to bulb or led mode. as a result, both load types are optimized in term s of switching and diagnosis behavior. it is designed to drive lamps up to 3*27w + 2*10w. product summary operating voltage power switch v bb 5.5 ? 28 v logic supply voltage v dd 3.8?5.5v over voltage protection v bb(az,min) 40 v maximum stand-by current at 25 c i bb(off) 3 a on-state resistance at t j = 150 c channel 0, 1, 2 channel 3, 4 r ds(on,max) 100 m ? 260 m ? spi access frequency f sclk(max) 2mhz
spoc - BTS5572E overview data sheet 4 rev. 1.0, 2008-05-15 configuration and status diagnosis are d one via spi. an 8 bit serial peripheral interface (spi) is used. the spi can be used in daisy chain configuration. the device provides a current sense signal per channel th at is multiplexed to the diagnosis pin is. it can be enabled and disabled via spi commands. an over load and over temperature flag is provided in the spi diagnosis word. a multiplexed switch bypass monitor provides short-circuit to v bb diagnosis. in order to use the same hardware, channels out0, out1 and out2 can be configured to bulb or led mode. the spoc - BTS5572E provides a fail-safe feature via a limp home input pin. the power transistors are built by n-channel vert ical power mosfets with c harge pumps. the device is monolithically in tegrated in smart technology. protective functions ? reverse battery protecti on with external components ? short circuit protection ? overload protection ? multi step current limitation ? thermal shutdown with latch and dynamic temperature sensor ? overvoltage protection ? loss of ground protection ? electrostatic discha rge protection (esd) diagnostic functions ? multiplexed proportional load current sense signal (is) ? enable function for current s ense signal configurable via spi ? high accuracy of current sense signal at wide load current range ? current sense ratio ( k ilis ) configurable for leds or bulbs ? very fast diagnosis in led mode (>2% duty cycle at 100 hz) ? feedback on over temperature and over load via spi ? multiplexed switch bypass monitor provides short circuit to v bb detection application specific functions ? fail-safe activation via lhi pin and control via input pins ? load type configuration via spi (bulbs or leds) for optimized load control applications ? high-side power switch for 12 v grounded loads in automotive applications ? especially designed for standard exterior lighting like tail light, brake light, parkin g light, license plate light, indicators and equivalent leds ? replaces electromechanical relays, fuses and discrete circuits
data sheet 5 rev. 1.0, 2008-05-15 spoc - BTS5572E block diagram 2blockdiagram figure 1 block diagram spoc - BTS5572E 4 3 2 1 channel 0 power supply driver logic gate control & charge pump clamp for inductive load load current lim itation load current sense temperature sensor esd protection in2 in3 in4 in0 in1 gnd spi current sense multiplexer is so sclk si cs lhi limp home control switch bypass monitor pwm control vbb out3 out2 out1 out0 out4 vdd
spoc - BTS5572E block diagram data sheet 6 rev. 1.0, 2008-05-15 2.1 terms the following figure shows all term s used in this data sheet. figure 2 terms in all tables of electrical characteri stics is valid: channel related symbols without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds0 ? v ds4 ). all spi register bits are marked as follows: addr.parameter (e.g. hwcr.ctl ). in spi register description, the values in bold letters (e.g. 0 ) are default values. terms_5.emf i in 0 v in 0 i in 1 v in 1 v so i in 2 v si i in 3 v bb v cs i is i bb in0 in1 in2 in3 is vbb i cs cs sclk v in 2 v in 3 v in 4 v dd i dd i so vdd so i in 4 in4 v is i lhi lh i i si si v lhi out0 i l0 out1 out3 out4 i l1 i l3 i l4 v out3 v out2 v ds3 v ds2 out2 i l2 gnd i gnd i sc l k v sc l k v out1 v out0 v ds1 v ds0 v out4 v ds4
data sheet 7 rev. 1.0, 2008-05-15 spoc - BTS5572E pin configuration 3 pin configuration 3.1 pin assignment spoc - BTS5572E figure 3 pin configuration pg-dso-36-36 wrsylhz 287 287 287 9%% qf 287 287 287 287 287 qf 287 287 287 287 287 qf 9%% qf &6 6&/. 6, 62 ,1 ,1 ,1 ,1 ,1 9%% h[srvhgsdgerwwrp /+, ,6 9'' *1' qf* qf* qf* qf
spoc - BTS5572E pin configuration data sheet 8 rev. 1.0, 2008-05-15 3.2 pin definitions and functions pin symbol i/o function power supply pins 19, 36, 37 1) 1) the exposed pad (pin 37) has to be connected to the pow er supply with a low impedance connection. the exposed pad must be connected with a low thermal resistance. vbb ? positive power supply for high-side power switch 2 vdd ? logic supply (5 v) 1 gnd ? ground connection parallel input pins (integrated pull- down, leave unused input pins unconnected) 7 in0 i input signal of channel 0 8 in1 i input signal of channel 1 9 in2 i input signal of channel 2 10 in3 i input signal of channel 3 11 in4 i input signal of channel 4 power output pins 32, 33, 34 2) 2) all outputs pins of each channel have to be connected. out0 o protected high-side power output of channel 0 29, 30, 31 2) out1 o protected high-side power output of channel 1 22, 23, 24 2) out2 o protected high-side power output of channel 2 27,28 2) out3 o protected high-side power output of channel 3 25,26 2) out4 o protected high-side power output of channel 4 spi & diagnosis pins 6 cs i chip select of spi interface (low active), integrated pull up 5 sclk i serial clock of spi interface 4 si i serial input of spi interface 3 so o serial output of spi interface 14 is o diagnosis output signal limp home pin (integrated pull-down, leave unused limp home pin unconnected) 13 lhi i limp home activation signal; active high not connected pin 12, 15, 20, 21, 35 n.c. ? not connected, internally not bonded 16, 17, 18 n.c.* ? not connected, inte rnally not bonded, shorted together
data sheet 9 rev. 1.0, 2008-05-15 spoc - BTS5572E electrical characteristics 4 electrical characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. supply voltage 4.1.1 power supply voltage v bb -0.3 28 v ? 4.1.2 logic supply voltage v dd -0.3 5.5 v ? 4.1.3 reverse polarity voltage according figure 21 - v bat(rev) ?16v t j(start) = 25 c t 2min. 2) 4.1.4 supply voltage for fu ll short circuit protection (single pulse) ( t j(0) = -40 c ? 150 c) v bb(sc) 020 v r ecu = 20m ? r cable = 16m ? /m l cable = 1h/m l = 0 or 5m 3) 4.1.5 voltage at power transistor v ds ?40v? 4.1.6 supply voltage for load dump protection v bb(ld) ?40v r i = 2 ? 4) t = 400ms 4.1.7 current through ground pin i gnd -100 25 ma t 2min. 4.1.8 current through v dd pin i dd -25 12 ma t 2min. power stages 4.1.9 load current i l - i l(lim) i l(lim) a 5) diagnosis pin 4.1.10 current through sense pin is i is -10 10 ma t 2min. input pins 4.1.11 voltage at input pins v in -0.3 8.0 v ? 4.1.12 current through input pins i in -0.75 -2.0 0.75 2.0 ma ? t 2min. spi pins 4.1.13 voltage at chip select pin v cs -0.3 5.7 v ? 4.1.14 current through chip select pin i cs -0.75 -2.0 0.75 2.0 ma ? t 2min. 4.1.15 voltage at serial input pin v si -0.3 5.7 v ? 4.1.16 current through serial input pin i si -0.75 -2.0 0.75 2.0 ma ? t 2min. 4.1.17 voltage at serial clock pin v sclk -0.3 5.7 v ? 4.1.18 current through serial clock pin i sclk -0.75 -2.0 0.75 2.0 ma ? t 2min. 4.1.19 current through serial output pin so i so -0.75 -2.0 0.75 2.0 ma ? t 2min. limp home pin 4.1.20 voltage at limp home input pin v lhi -0.3 8.0 v ?
spoc - BTS5572E electrical characteristics data sheet 10 rev. 1.0, 2008-05-15 note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.2 thermal resistance 4.1.21 current through limp home input pin i lhi -0.75 -2.0 0.75 2.0 ma ? t 2min. temperatures 4.1.22 junction temperature t j -40 150 c? 4.1.23 dynamic temperature increase while switching ? t j ?60k? 4.1.24 storage temperature t stg -55 150 c? esd susceptibility 4.1.25 esd resistivity out pins vs. vbb other pins incl. out vs. gnd v esd -4 -2 4 2 kv hbm 6) ? ? 1) not subject to production test, specified by design. 2) device mounted on a fr4 2s2p board according to jedec jesd51-2,-5,-7 at natural convection; the product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). where applicable, a thermal via array under the package contacted the first inner copper layer. 3) in accordance to aec q100-012 and aec q101-006. 4) r i is the internal resistance of the load dump pulse generator. 5) current limitation is a protection feature. operation in curr ent limitation is considered as ?outside? normal operating range . protection features are not designed for continuous repetitive operation. 6) esd resistivity, hbm according to eia/jesd 22-a 114b (1.5k ? , 100pf). pos. parameter symbol limit values unit conditions min. typ. max. 4.2.1 junction to case 1) 1) not subject to production test, specified by design. r thjc ??2k/w? 4.2.2 junction to ambient 1) r thja ?22?k/w 2) 2) device mounted on a fr4 2s2p board according to jedec jesd51-2,-5,-7 at natural convection; the product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). where applicable, a thermal via array under the package contacted the first inner copper layer. absolute maximum ratings (cont?d) 1) t j = -40 c to +150 c; all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max.
data sheet 11 rev. 1.0, 2008-05-15 spoc - BTS5572E power supply 5 power supply the spoc - BTS5572E is supplied by two supply voltages v bb and v dd . the v bb supply line is used by the power switches. the v dd supply line is used by the spi related circuitr y and for driving the so line. a capacitor between pins vdd and gnd is recommended as shown in figure 21 . there is a power-on reset function implemented for the v dd logic power supply. after start-up of the logic power supply, all spi registers are reset to their default values. the spi interface including da isy chain function is active as soon as v dd is provided in the specified range independent of v bb . the first spi transmission after a reset contains at pin so the read information from register out , the transmission error bit ter is set. 5.1 power supply modes the following table shows all possible power supply modes for v bb , v dd and the pin lhi. stand-by mode is entered as soon as the current sense multiplexer ( dcr.mux ) is in default (stand-by) position 1) . additionally, all thermal latches are cleared automatica lly. as soon as stand-by mode is entered, register hwcr.stb is set. to wake-up the device, the current sense multiplexer ( dcr.mux ) is programmed different to default (stand-by) position. idle mode parameters are valid, when all channels are switched off, but the current sense multiplexer is not in default position, and v dd supply is available. limp home (lhi = high) will wake-up the device and is working without v dd supply. as a result, all channels can be activated via the dedicated input pins. power supply modes off off spi on reset off limp home mode without spi normal operation limp home mode with spi 1) 1) spi read only. v bb 0v 0v 0v 0v 13.5v 13.5v 13.5v 13.5v v dd 0v 0v 5v 5v 0v 0v 5v 5v lhi 0v5v0v5v0v5v 0v 5v profet operating ? ? ? ? ? ??? limp home ????? ? ? ? spi (logic) ? ? ? reset reset reset ? reset stand-by current ? ? ? ? ? ? ? 2) 2) when dcr.mux = 111 b . ? idle current ?????? ? 3) 3) when all channels are in off-state and dcr.mux != 111 b . ? diagnosis ?????? ?? 4) 4) current sense disabled in limp home mode. 1) not affected by the inputs state
spoc - BTS5572E power supply data sheet 12 rev. 1.0, 2008-05-15 5.2 reset there are several reset triggers implemented in the device . they reset the spi registers and errors flags to their default values. the power stages are not affected by the reset signals. the first spi transmission a fter any kind of reset contains at pin so the read information from register out , the transmission error bit ter is set. power-on reset the power-on reset is released, when v dd voltage level is higher than v dd(min) . the spi interface can be accessed after wake up time t wu(po) . reset command there is a reset command available to reset all register bi ts of the register bank an d the diagnosis registers. as soon as hwcr.rst = 1, a reset is triggered equivalent to power-on reset. the spi interface can be accessed after transfer delay time t cs(td) . limp home mode in limp home mode, the spi write-registers are reset. ou tput outx will follow the input inx configuration only. for application example see figure 21 . the spi interface is operating normally, so the limp home register bit lhi as well as the error fl ags can be read, but an y write command will be ignored. to activate the limp home mode, lhi input pin voltage must be higher than v lhi(h) .
data sheet 13 rev. 1.0, 2008-05-15 spoc - BTS5572E power supply 5.3 electrical characteristics note: characteristics show the deviat ion of parameter at the given supply voltage and junction temperature. typical values show the ty pical parameters expected from manufacturing at v bb = 13.5 v, v dd = 4.3 v and t j =25 c. electrical characteristics power supply unless otherwise specified: v bb = 9 v to 16 v, v dd = 3.8v to 5.5v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. 5.3.1 operating voltage power switch v bb 5.5 ? 28 1) 1) not subject to production test, specified by design. v ? 5.3.2 stand-by current for whole device with loads i bb(stb) ? ? ? 0.5 ? ? 3 3 58 a v dd = 0 v v lhi = 0 v t j = 25 c t j 85 c 1) t j = 150 c 5.3.3 idle current for whole device with loads, all channels off. i bb(idle) ?38ma v dd = 5 v 2) dcr.mux = 110 b 2) in case of out.5 = 1 b increased current consumption. 5.3.4 logic supply voltage v dd 3.8 ? 5.5 v ? 5.3.5 logic supply current i dd ?55120 a v cs = 0 v f sclk = 0 hz 5.3.6 logic idle current i dd(idle) ?2050 a v cs = v dd f sclk = 0 hz chip in standby 5.3.7 operating current for whole device i gnd ? 1225ma f sclk = 0 hz lhi input characteristics 5.3.8 l-input level at pin lhi v lhi(l) -0.3 ? 1.0 v ? 5.3.9 h-input level at pin lhi v lhi(h) 2.6 ? 5.5 v ? 5.3.10 l-input current through pin lhi i lhi(l) 3?85 a v lhi = 0.4 v 5.3.11 h-input current through pin lhi i lhi(h) 73085 a v lhi = 5 v reset 5.3.12 power-on wake up time t wu(po) 500 s 1)
spoc - BTS5572E power supply data sheet 14 rev. 1.0, 2008-05-15 5.4 command description hwcr hardware configuration register w/r 1) rb 1) 1) w/r write/read, rb register bank, addr address addr 1) 3210 read1100xstbctl write11000rstctl field bits type description rst 1 w reset command 0 normal operation 1 execute reset command stb 1 r stand-by 0 device is awake 1 device is in stand-by mode
data sheet 15 rev. 1.0, 2008-05-15 spoc - BTS5572E power stages 6 power stages the high-side power stages are built by n-channel vert ical power mosfets (dmos) with charge pumps. there are five channels implemented in the device. each channel can be switched on via an input pin or via spi register out . channels 0, 1 and 2 provides a load type co nfiguration for bulbs or leds in register plcr . the load type configuration is allowed to be changed in off-state only. 6.1 output on-state resistance the on-state resistance r ds(on) depends on the supply voltage v bb as well as on the junction temperature t j . figure 4 shows those dependencies. the behavior in reverse polarity mode is described in section 11 . figure 4 typical on-state resistance 6.2 input circuit there are two ways of using the input pins in comb ination with the out regist er by programming the hwcr.pwm parameter. ? plcr.pwm = 0: a channel is switched on either by the according out register bit or the input pin. ? plcr.pwm = 1: a channel is switched on by the according out register bit only, when the input pin is high. in this configuration, a pwm signal can be given to the in put pin and the channel is ac tivated by the spi register out . figure 5 shows the complete input switch matrix. t j = 25 c 0 50 100 150 200 250 300 350 400 0 5 10 15 20 25 30 v bb [v] r ds(on) [m ? ] channel 0, 1, 2 (bulb) channel 0, 1, 2 (led) channel 3, 4 v bb = 13.5 v 0 50 100 150 200 250 300 350 -50 0 50 100 150 t j [c] r ds(on) [m ? ] channel 0, 1, 2 (bulb) channel 0, 1, 2 (led) channel 3, 4
spoc - BTS5572E power stages data sheet 16 rev. 1.0, 2008-05-15 figure 5 input switch matrix the current sink to ground ensures t hat the input signal is low in case of an open input pin. the zener diode protects the input circ uit against esd pulses. 6.3 power stage output the power stages are built to be us ed in high side configuration ( figure 6 ). figure 6 power stage output inputmatrix_5.emf in0 in1 in2 in3 in4 gate driver 2 gate driver 1 gate driver 0 gate driver 4 gate driver 3 & or out2 out1 out0 out4 out3 & or & or & or & or pwm i in 0 i in 1 i in 2 i in 3 i in 4 output .emf out gnd v out vbb vds v bb
data sheet 17 rev. 1.0, 2008-05-15 spoc - BTS5572E power stages the power dmos switches with a dedicated slope, which is optimized in terms of emc emission. figure 7 switching a load (resistive) when switching off inductive loads wi th high-side switches, the voltage v out drops below ground potential, because the inductance intends to continue driving the current. to prevent avalanche of the device, there is a voltage clamp mechanism implemented which limits th at negative output voltage to a certain level ( v ds(cl) ). see figure 6 for details. the maximum allo wed load inductance is limited. v out t switchon.emf t on t off t 90% 10% 70% d v / d t on 30% 70% d v / d t off 30% t delay(o n) t delay(o f f ) in / outx
spoc - BTS5572E power stages data sheet 18 rev. 1.0, 2008-05-15 6.4 electrical characteristics electrical characteristics power stages unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. output characteristics 6.4.1 on-state resistance r ds(on) m ? channel 0, 1, 2 ? ? ? ? 50 85 170 300 ? 100 ? 375 plcr.ledn = 0 1) t j = 25 c / i l = 2.6 a t j = 150 c / i l = 2.6 a plcr.ledn = 1 1) t j = 25 c / i l = 0.6 a t j = 150 c / i l = 0.6 a channel 3, 4 ? ? 110 200 ? 260 1) t j = 25 c / i l = 1.3 a t j = 150 c / i l = 1.3 a 6.4.2 output voltage drop lim itation at small load currents v ds(nl) mv channel 0, 1, 2 ?25? plcr.ledn = 0 i l = 35 ma channel 3, 4 ? 25 ? i l = 35 ma 6.4.3 output clamp v ds(cl) 40 47 54 v i l = 20 ma 2) 6.4.4 output leakage current per channel i l(off) a v in = 0 v or floating out.outn = 0 channel 0, 1, 2 ? ? 0.1 ? 10 40 stand-by idle channel 3, 4 ? ? 0.1 ? 8 40 stand-by idle 6.4.5 inverse current capability per channel -i l(ic) a 3) channel 0, 1, 2 ? 2.5 ? ? channel 3, 4 ? 1.0 ? ? input characteristics 6.4.6 l-input level v in(l) -0.3 ? 1.0 v ? 6.4.7 h-input level v in(h) 2.6 ? 5.5 v ? 6.4.8 l-input current i in(l) 32575 a v in = 0.4 v 6.4.9 h-input current i in(h) 10 40 75 a v in = 5 v
data sheet 19 rev. 1.0, 2008-05-15 spoc - BTS5572E power stages timings 6.4.10 turn-on delay to 10% v bb (logical propagation delay from input inx to output outx) t delay(on) s v bb = 13.5 v 1) channel 0, 1, 2 ?35? plcr.ledn = 0 r l = 6.8 ? channel 3, 4 ? 20 ? r l = 18 ? 6.4.11 turn-off delay to 90% v bb (logical propagation delay from input inx to output outx) t delay(off) s v bb = 13.5 v 1) channel 0, 1, 2 ?50? plcr.ledn = 0 r l = 6.8 ? channel 3, 4 ? 30 ? r l = 18 ? 6.4.12 turn-on time to 90% v bb t on s v bb = 13.5 v channel 0, 1, 2 ? ? ? ? 250 100 plcr.ledn = 0 r l = 6.8 ? plcr.ledn = 1 r l = 33 ? channel 3, 4 ? ? 150 r l = 18 ? 6.4.13 turn-off time to 10% v bb t off s v bb = 13.5 v channel 0, 1, 2 ? ? ? ? 290 100 plcr.ledn = 0 r l = 6.8 ? plcr.ledn = 1 r l = 33 ? channel 3, 4 ? ? 150 r l = 18 ? 6.4.14 turn-on slew rate 30% to 70% v bb d v / d t on v/ s v bb = 13.5 v channel 0, 1, 2 0.1 0.1 0.2 0.75 0.5 1.9 plcr.ledn = 0 r l = 6.8 ? plcr.ledn = 1 r l = 33 ? channel 3, 4 0.1 0.45 0.9 r l = 18 ? electrical characteristics power stages (cont?d) unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS5572E power stages data sheet 20 rev. 1.0, 2008-05-15 6.4.15 turn-off slew rate 70% to 30% v bb -d v / d t off v/ s v bb = 13.5 v channel 0, 1, 2 0.1 0.1 0.2 0.75 0.5 1.9 plcr.ledn = 0 r l = 6.8 ? plcr.ledn = 1 r l = 33 ? channel 3, 4 0.1 0.5 0.9 r l = 18 ? 1) not subject to production test, specified by design. 2) the voltage increase until the current is reached. 3) not subject to production test, specified by design. in case of inverse current ( v out > v bb ), the error flag err in the standard diagnosis of the affected channel is cleared. the inverse curre nt capability in on-state and off-state is defined for t j < t j(sc) and channel remains in same state (on-st ate or off-state). other channels can be affected (e.g. out latch due to junction temperature increase). electrical characteristics power stages (cont?d) unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 21 rev. 1.0, 2008-05-15 spoc - BTS5572E power stages 6.5 command description note: in case of out.5 = 1 b the device current consumption is increased. out output configuration registers w/r rb543210 read 0 x out4 out3 out2 out1 out0 write 0 0 out4 out3 out2 out1 out0 field bits type description outn n = 4 to 0 nrw set output mode for channel n 0 channel n is switched off 1 channel n is switched on plcr pwm and led-mode configuration register w/r rb addr 3 2 1 0 read/write 1 0 1 pwm led2 led1 led0 field bits type description pwm 3 rw pwm configuration 0 input signal or-combined with according out register bit 1 input signal and-comb ined with according out register bit ledn n = 2 to 0 nrw set led mode for channel n 0 channel n is in bulb mode 1 channel n is in led mode
spoc - BTS5572E protection functions data sheet 22 rev. 1.0, 2008-05-15 7 protection functions the device provides embedded protective functions, wh ich are designed to prevent ic destruction under fault conditions described in this data sheet. fault condit ions are considered as ?out side? normal operating range. protective functions are neither designed fo r continuous nor for repetitive operation. 7.1 over load protection the load current i l is limited by the device itself in case of over load or short circuit to ground. there are multiple steps of current limitation which are selected automatically depending on the voltage v ds across the power dmos. please note that the voltage at the out pin is v bb - v ds . please refer to following figures for details. figure 8 current limitation channels 0, 1, 2 (minimum values) figure 9 current limitation channels 3, 4 (minimum values) current limitatio n to the value i l(lim) is realized by increasing the resistan ce of the output channel, which leads to rapid temperature rise inside. currentlimitation012 .emf 5 101520 v ds 25 i l 5 10 15 20 25 wdlr.led = 0 wdlr.led = 1 current limit at ion34 . emf i l 5101520 v ds 25 2 4 6 8
data sheet 23 rev. 1.0, 2008-05-15 spoc - BTS5572E protection functions 7.2 over temperature protection each channel has its own temperature sensor. if the te mperature at the channel exceeds the thermal shutdown temperature t j(sc) , the channel will switch off and latch to prevent destruction (also in case of v dd = 0v). in order to reactivate the channel, the temperature at the out put must drop by at least the thermal hysteresis ? t j and the over temperature latch must be cleared by spi command hwcr.ctl = 1. all over temperature latches are cleared by spi command hwcr.ctl = 1. figure 10 shut down by over temperature additionally, all channels have their own dynamic temperature sensors. the dynamic temperature sensor improves short circuit robustness by limiting sudden increases in the junction temperature. the dynamic temperature sensor turns off the channel if its sudden temperature increase exceeds the dynamic temperature sensor threshold ? t j(sw) . please refer to the following figure for details. i l i is t i l(li m) t t err t overload .emf ctl = 1 in / outx
spoc - BTS5572E protection functions data sheet 24 rev. 1.0, 2008-05-15 figure 11 dynamic temperature sensor operations the err-flag will be set during dynamic temperature sensor shut down. it can be reset by read ing the err-flag. if the channel is still in dyna mic temperature sensor shut do wn, the err-flag will be set again. 7.3 reverse polarity protection in reverse polarity mode, power dissipation is caused by the intrinsic body diode of each dmos channel as well as each esd diode of the logic pins. the reverse current through the channels has to be limited by the connected loads. the current through the ground pin, sense pin is, the logic power supply pin v dd , the spi pins and the limp home input pin has to be limited as well (p lease refer to the maximum ratings listed on page 9 ). note: no protection mechanism like temperature protection or current limitation is active during reverse polarity. t t t t t ? t jsw ? t jsw ? t jsw i l(lim) i is t j delt at . emf err i l t j(sc) ctl = 1 in / outx
data sheet 25 rev. 1.0, 2008-05-15 spoc - BTS5572E protection functions 7.4 over voltage protection in addition to the output clamp for inductive loads as described in section 6.3 , there is a clamp mechanism available for over voltage protection. the current throug h the ground connection has to be limited during over voltage. please note that in case of over voltage the pin gnd might have a high vo ltage offset to the module ground. 7.5 loss of ground in case of complete loss of the device ground conne ctions, but connected load ground, the spoc - BTS5572E securely changes to or stays in off-state. 7.6 loss of v bb in case of loss of v bb connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path from v bb to ground. when a diode is used in the ground path for reverse polarity reason, the ground con nection is not available for demagnet ization. then for example, a resistor can be placed in parallel to the diode or a suppressor diode can be used between v bb and gnd.
spoc - BTS5572E protection functions data sheet 26 rev. 1.0, 2008-05-15 7.7 electrical characteristics electrical characteri stics protection functions unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. over load protection 7.7.1 load current limitation i l(lim) a v ds = 7 v channel 0, 1, 2 24 ? 40 plcr.ledn = 0 1) 1) for t j = 150 c, not subject to production test. device will shutdo wn due to the maximum junction temperature sensor. 6?12 plcr.ledn = 1 1) channel 3, 4 8 ? 18 1) over temperature protection 7.7.2 thermal shut down temperature t j(sc) 150 170 190 c 2) 7.7.3 thermal hysteresis ? t j ?7?k 2) 2) not subject to production test, specified by design. 7.7.4 dynamic temperature increase limitation while switching ? t jsw ?60?k 2) over voltage 7.7.5 overvoltage protection v bb(az) 40 47 54 v i bb = 4 ma
data sheet 27 rev. 1.0, 2008-05-15 spoc - BTS5572E protection functions 7.8 command description hwcr hardware configuration register w/r rb addr 3 2 1 0 write 1 1 0 0 0 rst ctl field bits type description ctl 0 rw clear thermal latch 0 thermal latches are untouched 1 command: clear all thermal latches
spoc - BTS5572E diagnosis data sheet 28 rev. 1.0, 2008-05-15 8 diagnosis for diagnosis purpose, the spoc - BTS5572E provides a current sense signal at pin is and the diagnosis word via spi. there is a current sense multiplexer implemented that is controlled via spi. the sense signal can also be disabled by spi command. a switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. please refer to figure 12 for details. figure 12 block diagram: diagnosis channel 0 load current sense dia gno sis_5.e m f r is i is 0 current sense multiplexer is t gate control load current limitation latch tem perature sensor err0 or latch dcr.mux v bb v ds(sb) sbm dcr. out4 out3 out2 out1 out0 vbb
data sheet 29 rev. 1.0, 2008-05-15 spoc - BTS5572E diagnosis for diagnosis feedback at differen t operation modes, please see table 1 . 8.1 diagnosis word at spi the standard diagnosis at the spi in terface provides information about each channel. the error flags, an or combination of the over temperature flags and the over lo ad monitoring signals are provided in the spi standard diagnosis bits errn . the over load monitoring signals are latched in the erro r flags and cleared each time the standard diagnosis is transmitted via spi. in detail, they are cleared between the second and third raising edge of the sclk signal. the over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control block. the latches are cleared by spi command hwcr.ctl . please note: the over temperature info rmation is latched twice. when trans mitting a clear thermal latch command ( hwcr.ctl ), the error flag is cleared during command transmis sion of the next spi frame and ready for latching after the third raising edge of the sclk signal. as a result, the first standard diagnosis information after a ctl command will indicate a failure mode at the previously af fected channels although t he thermal latches have been cleared already. in case of continuous over load, the error flags are set again imme diately because of the over load monitoring signal. table 1 operation modes 1) 1) l = low level, h = high level, z = high impedance, pot ential depends on leakage currents and external circuit. x = undefined. operation mode input level out.outn output level v out current sense i is error flag errn 2) 2) the error flags are latched until they are tran smitted in the standard diagnosis word via spi. dcr. sbm normal operation (off) l / 0 (off-state) gnd z 0 1 short circuit to gnd gnd z 0 1 thermal shut down z z 0 3) x short circuit to v bb v bb z 0 0 open load z z 0 x normal operation (on) h / 1 (on-state) ~ v bb i l / k ilis 00 current limitation < v bb z1 x short circuit to gnd ~gnd z 1 1 dynamic temperature sensor shut down z z 1 x thermal shut down z z 1 3) 3) the over temperature flag is set latched (in off states also) and can be cleared by spi command hwcr.ctl. x short circuit to v bb v bb < i l / k ilis 00 open load v bb z0 0
spoc - BTS5572E diagnosis data sheet 30 rev. 1.0, 2008-05-15 8.2 load current sense diagnosis there is a current sense signal available at pin is which provides a current proportional to the load current of one selected channel. the selection is done by a multiplexer which is configured via spi. current sense signal the current sense signal (ratio k ilis = i l / i s ) is provided as long as no failure mode occurs.the ratio k ilis can be adjusted to the load type (led or bulb) via spi register plcr for channels 0 to 2. usually a resistor r is is connected to the current sense pin. it is recommended to use resistors 2.5 k ?< r is < 7k ? . a typical value is 3.3 k ? . figure 13 current sense ratio k ilis channel 0, 1, 2 bulb and led mode 1) 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 012345 load current / proportion of i lnom normalized k ilis value kilis bulb max kilis bulb typ kilis bulb min kilis led max kilis led typ kilis led min
data sheet 31 rev. 1.0, 2008-05-15 spoc - BTS5572E diagnosis figure 14 current sense ratio k ilis channel 3, 4 1) in case of over current as well as over temperature, th e current sense signal of the affected channel is switched off. to distinguish between over temperature and over load, the spi diagnosis word can be used. whereas the over load flag is cleared every time the diagnosis is trans mitted, the over temperature flag is cleared by a dedicated spi command ( hwcr.ctl ). details about timings between the current sense signal i is and the output voltage v out and the load current i l can be found in figure 15 . figure 15 timing of current sense signal 1) the curves show the behavior based on characterization dat a. the marked points are guaranteed in this data sheet in section 8.4 (position 8.4.1 ). 0 500 1000 1500 2000 2500 3000 3500 4000 0 0,5 1 1,5 2 2,5 load current / proportion of i lnom normalized k ilis value kilis bulb max kilis bulb typ kilis bulb min sensetiming.emf in v out i is t t t i l t on t on t sis(on) t sis(lc) off t off t dis (off) off
spoc - BTS5572E diagnosis data sheet 32 rev. 1.0, 2008-05-15 current sense multiplexer there is a current sense multiplexer implemented in th e spoc - BTS5572E that routes the sense current of the selected channel to the diagnosis pin is. the channel is selected via spi register dcr.mux . the sense current also can be disabled by spi register dcr.mux . for details on timing of the current sense multiplexer, please refer to figure 16 . figure 16 timing of current sense multiplexer 8.3 switch bypass diagnosis to detect short circuit to v bb , there is a switch bypass monitor implemente d. in case of short circuit between the output pin out and v bb in on-state, the curr ent will flow through the power transistor as we ll as through the short circuit (bypass) with undefined ratio. as a result, the current sense signal will show lower values than expected by the load current. in o ff-state, the outp ut voltage will stay close to v bb potential which means a small v ds . the switch bypass monitor compares the voltage v ds across the power transistor of that channel which is selected by the current sense multiplexer ( dcr.mux ) with threshold v ds(sb) . the result of comparison can be read in spi register dcr.sbm . m uxtim ing.em f cs i is t t 000 dcr.mux 001 110 110 t sis(en) t sis(mux) t dis(mux)
data sheet 33 rev. 1.0, 2008-05-15 spoc - BTS5572E diagnosis 8.4 electrical characteristics unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. load current sense 8.4.1 current sense ratio k ilis channel 0, 1, 2 (bulb): plcr.ledn = 0 0.600 a 1.3 a 2.6 a 4.0 a 2450 2450 2700 2700 3100 3100 3100 3100 3900 3700 3500 3500 ? ? ? ? channel 0, 1, 2 (led): plcr.ledn = 1 0.020 a 0.050 a 0.300 a 0.600 a 1.0 a 500 590 680 730 750 950 910 830 830 830 1400 1250 990 930 910 ? ? ? ? ? channel 3, 4: 0.020 a 0.050 a 0.150 a 0.300 a 0.600 a 1.3 a 2.0 a 800 1000 1200 1250 1250 1350 1370 1800 1800 1700 1600 1550 1550 1550 2750 2400 2200 1950 1850 1750 1730 ? ? ? ? ? ? ? 8.4.2 current sense voltage limitation v is(lim) 0.9 v dd v dd 1.1 v dd v i is = 1 ma
spoc - BTS5572E diagnosis data sheet 34 rev. 1.0, 2008-05-15 8.4.3 current sense leakage / offset current i is(en) ??1 a i l = 0 dcr.mux = 000 b 8.4.4 current sense leakage, while diagnosis disabled i is(dis) ??1 a dcr.mux = 110 b 8.4.5 current sense settling time after channel activation channel 0, 1, 2 t sis(on) ??300 s v bb = 13.5 v r is = 3.3 k ? plcr.ledn = 0 r l = 6.8 ? ??115 plcr.ledn = 1 r l = 33 ? channel 3, 4 ? ? 180 r l = 18 ? 8.4.6 current sense desettling time after channel deactivation t dis(off) ??25 s v bb = 13.5 v 1) r is = 3.3 k ? plcr.ledn = 0 ??25 plcr.ledn = 1 8.4.7 current sense settling time after change of load current channel 0, 1, 2 t sis(lc) ??30 s v bb = 13.5 v 1) r is = 3.3 k ? plcr.ledn = 0 i l = 2.6 a to 1.3 a channel 3, 4 ? ? 30 i l = 1.3 a to 0.6 a 8.4.8 current sense settling time after current sense activation t sis(en) ??25 s r is = 3.3 k ? dcr.mux : 110 b -> 000 b 8.4.9 current sense settling time after multiplexer channel change t sis(mux) ??30 s r is = 3.3 k ? dcr.mux : 000 b -> 001 b 8.4.10 current sense deactivation time t dis(mux) ??25 s r is = 3.3 k ? dcr.mux : 1) 001 b -> 110 b switch bypass monitor 8.4.11 switch bypass monitor threshold v ds(sb) 0.7? 2.5v ? 1) not subject to production test, specified by design. unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 35 rev. 1.0, 2008-05-15 spoc - BTS5572E diagnosis 8.5 command description dcr diagnosis control register w/r rb addr 3 2 1 0 read 1 1 1 sbm mux write 1 1 1 0 mux input level out.outn field bits type description l / 0 (off-state) mux 2:0 rw set current sense multiplexer configuration 000 is pin is high impedance 001 is pin is high impedance 010 is pin is high impedance 011 is pin is high impedance 100 is pin is high impedance 101 is pin is high impedance 110 is pin is high impedance 111 stand-by mode (is pin is high impedance) sbm 3 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb) 1) invalid in stand-by mode h / 1 (on-state) mux 2:0 rw set current sense multiplexer configuration 000 current sense of channel 0 is routed to is pin 001 current sense of channel 1 is routed to is pin 010 current sense of channel 2 is routed to is pin 011 current sense of channel 3 is routed to is pin 100 current sense of channel 4 is routed to is pin 101 is pin is high impedance 110 is pin is high impedance 111 stand-by mode (is pin is high impedance) sbm 3 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb)
spoc - BTS5572E diagnosis data sheet 36 rev. 1.0, 2008-05-15 standard diagnosis cs76543210 ter 0 lhi x err4 err3 err2 err1 err0 field bits type description errn n = 4 to 0 nr error flag channel n 0 normal operation 1 failure mode occurred
data sheet 37 rev. 1.0, 2008-05-15 spoc - BTS5572E serial peripheral interface (spi) 9 serial peripheral interface (spi) the serial peripheral interface (spi) is a full duplex sync hronous serial slave interface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the rate given by sclk. the falling edge of cs indicates the beginning of an access. da ta is sampled in on line si at the falling edge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferr ed. the interface provides daisy chain capability. figure 17 serial peripheral interface 9.1 spi signal description cs - chip select: the system micro controller selects the spoc - BTS5572E by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the requested information is transferred into the shift register. ? so changes from high impedance state to high or lo w state depending on the logi c or combination between the transmission error flag ( ter ) and the signal level at pin si. as a re sult, even in daisy chain configuration, a high signal indicates a faulty transmission. this inform ation stays available to the first rising edge of sclk. cs low to high transition: ? command decoding is only done, when after the falling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. in case of faul ty transmission, the transmission error flag ( ter ) is set and the command is ignored. ? data from shift register is transferred into the addressed register. sclk - serial clock: this input pin clocks the in ternal shift register. the serial input (si) transfers da ta into the shift register on the falling edge of sclk while the serial output (s o) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shift-in at this pin, the most significant bit first. si information is read on the falling edge of sclk. the input data consists of two parts, co ntrol bits followed by dat a bits. please refer to section 9.5 for further information. lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 cs msb msb so si cs sclk time spi.emf
spoc - BTS5572E serial peripheral interface (spi) data sheet 38 rev. 1.0, 2008-05-15 so serial output: data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appe ar at the so pin following the risi ng edge of sclk. please refer to section 9.5 for further information. 9.2 daisy chain capability the spi of spoc - BTS5572E provides dais y chain capability. in th is configuration several devices are activated by the same cs signal mcs . the si line of one device is connecte d with the so line of another device (see figure 18 ), in order to build a chain. the ends of the chain are connected with the output and input of the master device, mo and mi respectively. the ma ster device provides the master cl ock mclk which is connected to the sclk line of each device in the chain. figure 18 daisy chain configuration in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out occurs at the so pin. after eight sclk cyc les, the data transfer for one device has been finished. in single chip configuration, the cs line must turn high to make the devic e accept the transferred data. in daisy chain configuration, the data shifted out at device 1 ha s been shifted in to device 2. when using three devices in daisy chain, three times eight bits have to be shifted through the devices. after that, the mcs line must turn high (see figure 19 ). figure 19 data transfer in daisy chain configuration si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _daisychain . emf mi mo mcs mclk si device 3 si device 2 si device 1 s o devi ce 3 s o devi ce 2 s o devi ce 1 time spi _dasychain2. emf
data sheet 39 rev. 1.0, 2008-05-15 spoc - BTS5572E serial peripheral interface (spi) 9.3 timing diagrams figure 20 timing diagram spi access 9.4 electrical characteristics unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c, v dd = 3.8 v to 5.5 v typical values: v bb = 13.5 v, t j = 25 c, v dd = 4.3 v pos. parameter symbol limit values unit test conditions min. typ. max. input characteristics (cs , sclk, si) 9.4.1 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) -0.3 -0.3 -0.3 ? ? ? 1.0 1.0 1.0 v v dd = 4.3 v ? ? ? 9.4.2 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 2.6 2.6 2.6 ? ? ? 5.5 5.5 5.5 v v dd = 4.3 v ? ? ? 9.4.3 l-input pull-up current at cs pin -i cs(l) 10 30 85 a v dd = 4.3 v v cs = 0 v 9.4.4 h-input pull-up current at cs pin -i cs(h) 3?85 a v dd = 4.3 v v cs = 2.6 v 9.4.5 l-input pull-down current at pin sclk si i sclk(l) i si(l) 3 3 ? ? 75 75 a v dd = 4.3 v v sclk = 0.4 v v si = 0.4 v 9.4.6 h-input pull-do wn current at pin sclk si i sclk(h) i si(h) 10 10 30 30 75 75 a v dd = 4.3 v v sclk = 4.3 v v si = 4.3 v output characteristics (so) 9.4.7 l level output voltage v so(l) 0?0.5v i so = -0.5 ma cs sclk si t cs(lead) t cs( td ) t cs( l a g ) t scl k( h) t scl k( l ) t scl k( p) t si( su ) t si( h ) so t so( v) t so( e n ) t so( d is) 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd spi t iming. emf
spoc - BTS5572E serial peripheral interface (spi) data sheet 40 rev. 1.0, 2008-05-15 9.4.8 h level output voltage v so(h) v dd - 0.5 v ? v dd v i so = 0.5 ma v dd = 4.3 v 9.4.9 output tristate leakage current i so(off) -10 ? 10 a v cs = v dd timings 9.4.10 serial clock frequency f sclk 0?2mhz? 9.4.11 serial clock period t sclk(p) 500 ? ? ns ? 9.4.12 serial clock high time t sclk(h) 250 ? ? ns ? 9.4.13 serial clock low time t sclk(l) 250 ? ? ns ? 9.4.14 enable lead time (falling cs to rising sclk) t cs(lead) 1?? s? 9.4.15 enable lag time (falling sclk to rising cs ) t cs(lag) 1?? s? 9.4.16 transfer delay time (rising cs to falling cs ) t cs(td) 1?? s? 9.4.17 data setup time (required time si to falling sclk) t si(su) 100 ? ? ns ? 9.4.18 data hold time (falling sclk to si) t si(h) 100 ? ? ns ? 9.4.19 output enable time (falling cs to so valid) t so(en) ??1 s c l = 20 pf 1) 9.4.20 output disable time (rising cs to so tri-state) t so(dis) ??1 s c l = 20 pf 1) 9.4.21 output data valid time with capacitive load t so(v) ? ? 250 ns c l = 20 pf 1) 1) not subject to production test, specified by design. unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c, v dd = 3.8 v to 5.5 v typical values: v bb = 13.5 v, t j = 25 c, v dd = 4.3 v pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 41 rev. 1.0, 2008-05-15 spoc - BTS5572E serial peripheral interface (spi) 9.5 spi protocol note: reading a register needs two spi frames. in the first frame the rd command is sent. in the second frame the output at spi signal so will cont ain the requested information. a ne w command can be executed in the second frame. cs 1) 1) the so pin shows this information between cs hi -> lo and first sclk lo -> hi transition. 76543210 write out register si 1 0 0 out4 out3 out2 out1 out0 read out register si 00xxxxx0 write configuration register si 1 1 addr data read configuration register si 0 1 addr x x x 0 read standard diagnosis si 0xxxxxx1 standard diagnosis so ter 0 lhi x err4 err3 err2 err1 err0 second frame of read command so ter 1 0 0 out4 out3 out2 out1 out0 so ter 1 1 addr data field bits type description rb 6 rw register bank 0 read / write to the outx channel 1 read / write to the other register ter cs r transmission error 0 previous transmission was successful (modulo 8 clocks received) 1 previous transmission failed or first transmission after reset outx x = 4 to 0 xrw output control register of channel x 0 off 1on addr 5:4 rw address pointer to register for read and write command data 3:0 rw data data written to or read from register selected by address addr lhi 6 r limp home enable 0 l-input signal at pin lhi 1 h-input signal at pin lhi errx x = 4 to 0 xr diagnosis of channel x 0 no failure 1 over temperature, over load or short circuit
spoc - BTS5572E serial peripheral interface (spi) data sheet 42 rev. 1.0, 2008-05-15 9.6 register overview name w/r rb 5 4 3 2 1 0 default 1) 1) the default values are set after reset. out w/r 0 0 out4 out3 out2 out1 out0 00 h name w/r rb addr 3 2 1 0 default 1) plcr w/r 1 0 1 pwm led2 led1 led0 00 h hwcr r 1 1 0 0 x stb ctl 02 h w 11000rstctl - dcr r 1 1 1 sbm mux 07 h w1110 mux -
data sheet 43 rev. 1.0, 2008-05-15 spoc - BTS5572E application description 10 application description figure 21 application circuit example * c e.g. xc2267 vss spi vbb lhi gnd out3 out2 out1 out0 out4 gnd limp_home vcc v bat ad 3.9k ? 3.9k ? 3.9k ? 3.9k ? 5v vdd vdd 100nf 500 ? limp_home 8k ? 8k ? 3.3k ? 1k ? 1nf gpio gpio so sclk si cs is in1 in2 in3 in4 in0 circuit_5.emf spi 8k ? 10nf.. 100nf 27 w 27 w 27 w 10 w 10 w 68nf * for filtering and protection purposes
spoc - BTS5572E package outlines spoc - BTS5572E data sheet 44 rev. 1.0, 2008-05-15 11 package outlines spoc - BTS5572E figure 22 pg-dso-36-36 (plastic dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-dso-36-36-po v01 exposed diepad 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion of 0.05 max. per side (spherical shape) package index marking ejector mark leadframe (flat shape) ex ey ex 0.65 bottom view 0 ... 0.1 ey 0.35 x 45 8 max. 0.17 m a-b d c 36x 0.08 0.33 2) c 0.1 2.45 -0.2 2.55 max. -0.2 7.6 1) 0.2 0.7 0.3 10.3 d 0.23 +0.09 118 19 36 a b -0.2 12.8 1) 36 19 18 1 index marking (spherical shape) exposed diepad dimensions pg-dso-36-36 c66065-a6940-c016 6.8 4.2 for further information on alternative packages, please visit our website: http://www.infineon.com/packages .
data sheet 45 rev. 1.0, 2008-05-15 spoc - BTS5572E revision history 12 revision history revision date changes 1.0 2008-05-15 initial revision
edition 2008-05-15 published by infineon technologies ag 81726 munich, germany ? 2008 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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